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256k x 36/512k x 18 pipelined sram with nobl? architecture cy7c1354bv25 cy7c1356bv25 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05292 rev. *e revised august 10, 2004 features ? pin-compatible and functionally equivalent to zbt? ? supports 225-mhz bus operations with zero wait states ? available speed grades are 225, 200 and 166 mhz ? internally self-time d output buffer cont rol to eliminate the need to use asynchronous oe ? fully registered (inputs and outputs) for pipelined operation ? byte write capability ? single 2.5v power supply ? fast clock-to-output times ? 2.8 ns (for 225-mhz device) ? 3.2ns (for 200-mhz device) ? 3.5 ns (for 166-mhz device) ? clock enable (cen ) pin to suspend operation ? synchronous self-timed writes ? available in 100 tqfp, 119 bga, and 165 fbga packag- es ? ieee 1149.1 jtag boundary scan ? burst capability?linear or interleaved burst order ? ?zz? sleep mode option and stop clock option functional description the cy7c1354bv25 and cy7c1356bv25 are 2.5v, 256k x 36 and 512k x 18 synchronous pipelined burst srams with no bus latency? (nobl ?) logic, respectively. they are designed to support unlimited true back-to-back read/write operations with no wait states. the cy7c1354bv25 and cy7c1356bv25 are equipped with the advanced (nobl) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically improves the thr oughput of data in systems that require frequent write/read transitions. the cy7c1354bv25 and cy7c1356bv25 are pin compatible and functionally equivalent to zbt devices. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by t he rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. write operations are controlled by the byte write selects (bw a ?bw d for cy7c1354bv25 and bw a ?bw b for cy7c1356bv25) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output three-state co ntrol. in order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s e clk c en write drivers bw c bw d zz sleep control o u t p u t r e g i s t e r s logic block diagram-cy7c1354bv25 (256k x 36)
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 2 of 27 selection guide cy7c1354bv25-225 CY7C1356BV25-225 cy7c1354bv25-200 cy7c1356bv25-200 cy7c1354bv25-166 cy7c1356bv25-166 unit maximum access time 2.8 3.2 3.5 ns maximum operating current 250 220 180 ma maximum cmos standby current 35 35 35 ma shaded areas contain advance information. plea se contact your local cypress sales repr esentative for availability of these part s. a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e clk c en write drivers zz sleep control logic block diagram-cy7c1356bv25 (512k x 18)
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 3 of 27 pin configurations a a a a a 1 a 0 v ss v dd a a a a a a v ddq v ss dqb dqb dqb v ss v ddq dqb dqb v ss nc v dd dqa dqa v ddq v ss dqa dqa v ss v ddq v ddq v ss dqc dqc v ss v ddq dqc v dd v ss dqd dqd v ddq v ss dqd dqd dqd v ss v ddq a a ce 1 ce 2 bw a ce 3 v dd v ss clk we cen oe e(18) a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz cy7c1354bv25 100-pin tqfp packages a a a a a 1 a 0 v ss v dd a a a a a a a nc nc v ddq v ss nc dqp a dqa dqa v ss v ddq dqa dqa v ss nc v dd dqa dqa v ddq v ss dqa dqa nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb v dd v ss dqb dqb v ddq v ss dqb dqb dqpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe e(18) a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode cy7c1356bv25 bw d mode bw c dqc dqc dqc dqc dqpc dqd dqd dqd dqpb dqb dqa dqa dqa dqa dqpa dqb dqb (256k 36) (512k 18) bw b nc nc nc dqc nc e(288) e(144) e(72) e(36) e(288) e(144) e(72) e(36) dqpd
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 4 of 27 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u dq a v ddq nc nc dq c dq d dq c dq d aa aa e(18) v ddq ce 2 a v ddq v ddq v ddq v ddq nc nc a dq c dq c dq d dq d tms v dd a e(72) dqp d a a adv/ld ace 3 nc v dd aanc v ss v ss nc dqp b dq b dq b dq a dq b dq b dq a dq a nc tdi tdo v ddq tck v ss v ss v ss nc v ss v ss v ss v ss mode ce 1 v ss oe v ss v ddq bw c a v ss we v ddq v dd nc v dd v ss clk nc bw a cen v ss v ddq v ss zz nc a a a1 a0 v ss v dd nc cy7c1354bv25 (256k 36) ? 14 22 bga dqp c dq b a e(36) dq c dq b dq c dq c dq c dq b dq b dq a dq a dq a dq a dqp a dq d dq d dq d dq d bw d 119-ball bga pinout bw b 234567 1 a b c d e f g h j k l m n p r t u e(36) dq a v ddq nc nc nc dq b dq b dq b dq b aa aa e(18) v ddq ce 2 a nc v ddq nc v ddq v ddq v ddq nc nc nc e(72) a dq b dq b dq b dq b nc nc nc nc tms v dd a a dqp b a a adv/ld a ce 3 nc v dd aanc v ss v ss nc nc dqp a dq a dq a dq a dq a dq a dq a dq a nc tdi tdo v ddq tck v ss v ss v ss nc v ss v ss v ss v ss v ss mode ce 1 v ss nc oe v ss v ddq bw b av ss nc v ss we nc v ddq v dd nc v dd nc v ss clk nc nc bw a cen v ss nc v ddq v ss nc zz nc a a a a1 a0 v ss nc v dd nc cy7c1356bv25 (512k x 18)?14 x 22 bga
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 5 of 27 pin configurations (continued) 234 567 1 a b c d e f g h j k l m n p r tdo e(288) nc dqp c dq c dqp d nc dq d a ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d e(36) e(72) v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 nc a a adv/ld nc oe e(18) a e(144) v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a 234 567 1 a b c d e f g h j k l m n p r tdo e(288) nc nc nc dqp b nc dq b a ce 1 nc ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc e(36) e(72) v ddq nc bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 nc a a adv/ld a oe e(18) a e(144) v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a cy7c1356bv25 (512k 18) ? 13 15 fbga cy7c1354bv25 (256k 36) ? 13 15 fbga 165-ball fbga pinout
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 6 of 27 pin definitions pin name i/o type pin description a0, a1, a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. bw a, bw b, bw c, bw d input- synchronous byte write select inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bw a controls dq a and dqp a , bw b controls dq b and dqp b , bw c controls dq c and dqp c , bw d controls dq d and dqp d . we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input used to advance the on-chip address counter or load a new address . when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input- clock clock input . used to capture all synchronous inpu ts to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pi ns. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/ o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. dq a, dq b, dq c, dq d i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [17:0] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ?dq d are placed in a three-state condition. the outputs are aut omatically three-stated during the data portion of a write sequence, during the fi rst clock when emerging from a deselected state, and when the device is deselect ed, regardless of the state of oe . dqp a, dqp b, dqp c dqp d i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq [31:0] . during write sequences, dqp a is controlled by bw a , dqp b is controlled by bw b , dqp c is controlled by bw c , and dqp d is controlled by bw d . mode input strap pin mode input . selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear bur st order. mode shoul d not change states during operation. when left floating mode will default high, to an interleaved burst order. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. tms test mode select synchronous this pin controls the test access port state machine . sampled on the rising edge of tck. tck jtag-clock clock input to the jtag circuitry . v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry .
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 7 of 27 functional overview the cy7c1354bv25 and cy7c1356bv25 are synchronous-pipelined burst nobl srams designed specifi- cally to eliminate wait states during write/read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 3.2 ns (200-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bw [d:a] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clo ck rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the ou tput register. at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.2 ns (200-mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. during the second clock, a subsequent oper ation (read/write/deselect) can be initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. burst read accesses the cy7c1354bv25 and cy7c1356bv25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequ ence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap-around when incremented suffi- ciently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated w hen the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to a 0 ?a 16 is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise the data lines are automatically three-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dqp (dq a,b,c,d /dqp a,b,c,d for cy7c1354bv25 and dq a,b /dqp a,b for cy7c1356bv25). in addition, the address for the subse- quent access (read/write/deselect) is latched into the address register (provided the appropriate control signals are asserted). on the next clock rise the data presented to dq and dqp (dq a,b,c,d /dqp a,b,c,d for cy7c1354bv25 & dq a,b /dqp a,b for cy7c1356bv25) (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. the data written during the writ e operation is controlled by bw (bw a,b,c,d for cy7c1354bv25 and bw a,b for cy7c1356bv25) signals. the cy7c1354bv25/ cy7c1356bv25 provides byte write capability that is described in the write cycle description table. asserting the write enable input (we ) with the selected byte write select (bw ) input will selectively write to only the desired bytes. bytes not select ed during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. v ss ground ground for the device . should be connected to ground of the system. nc ? no connects . this pin is not connected to the die. e(18,36,72, 144, 288) ? these pins are not connected . they will be used for expansion to the 18m, 36m, 72m, 144m and 288m densities. zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time critical ?sleep? condition with data integrity preserved. duri ng normal operation, this pin can be connected to vss or left floating. pin definitions (continued) pin name i/o type pin description
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 8 of 27 because the cy7c1354bv25 and cy7c1356bv25 are common i/o devices, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dq and dqp (dq a,b,c,d /dqp a,b,c,d for cy7c1354bv25 and dq a,b /dqp a,b for cy7c1356bv25) inputs. doing so will three-state the output drivers. as a safety precaution, dq and dqp (dq a,b,c,d / dqp a,b,c,d for cy7c1354bv25 and dq a,b /dqp a,b for cy7c1356bv25) are automatically three-stated during the data portion of a wr ite cycle, regardless of the state of oe . burst write accesses the cy7c1354bv25/cy7c1356bv25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. adv/ld must be driven low in order to load the initial addr ess, as described in the single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incre- mented. the correct bw (bw a,b,c,d for cy7c1354bv25 and bw a,b for cy7c1356bv25) inputs must be driven in each cycle of the burst write in orde r to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. zz mode electrical characteristics parameter description test conditions min. max unit i ddzz sleep mode standby current zz > v dd ? 0.2v 35 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep curre nt this parameter is sampled 0 ns truth table [1, 2, 3, 4, 5, 6, 7] operation address used ce zz adv/ ld we bwx oe cen clk dq deselect cycle none h l l x x x l l-h three-state continue deselect cycle none x l h x x x l l-h three-state read cycle (begin burst) exte rnal l l l h x l l l-h data out (q) read cycle (continue burst) next x l h x x l l l-h data out (q) nop/dummy read (begin burst) external l l l h x h l l-h three-state dummy read (continue burst) next x l h x x h l l-h three-state write cycle (begin burst) external l l l l l x l l-h data in (d) write cycle (continue burst) next x l h x l x l l-h data in (d) nop/write abort (begin burs t) none l l l l h x l l-h three-state write abort (continue burst) next x l h x h x l l-h three-state ignore clock edge (stall) current x l x x x x h l-h - sleep mode none x h x x x x x x three-state notes: 1. x = ?don't care?, 1 = logic high, 0 = logic low, ce stands for all chip enables active. bw x = 0 signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 2. write is defined by we and bw [a:d] . see write cycle description table for details. 3. when a write cycle is detected, all i/os are three-stated, even during byte writes. 4. the dq and dqp pins are controlled by the current cycle and the oe signal. 5. cen = 1 inserts wait states. 6. device will power-up deselected and the i/os in a three-state condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dqs a nd dqp [a:d] = three-state when oe is inactive or when the device is deselected, and dqs = data when oe is active
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 9 of 27 interleaved burst address table (mode = floating or v dd ) first address second address third address fourth address a[1:0] a[1:0] a[1:0] a[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address second address third address fourth address a[1:0] a[1:0] a[1:0] a[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 partial write cycle description [1, 2, 3, 8] function (cy7c1354bv25) we bw d bw c bw b bw a read h x x x x write ?no bytes written l h h h h write byte a? (dq a and dqp a) lhhhl write byte b ? (dq b and dqp b) lhhlh write bytes b, a l h h l l write byte c ? (dq c and dqp c) lhlhh write bytes c, a l h l h l write bytes c, b l h l l h write bytes c, b, a l h l l l write byte d ? (dq d and dqp d) llhhh write bytes d, a l l h h l write bytes d, b llhlh write bytes d, b, a l l h l l write bytes d, c l l l h h write bytes d, c, a l l l h l write bytes d, c, b l l l l h write all bytes l l l l l function (cy7c1356bv25) we bw b bw a read hx x write ? no bytes written l h h write byte a ? (dq a and dqp a) lhl write byte b ? (dq b and dqp b) llh write both bytes l l l note: 8. table only lists a partial listing of the byte write combinations. any combination of bw [a:d] is valid. appropriate write will be done based on which byte write is active.
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 10 of 27 ieee 1149.1 serial boundary scan (jtag) the cy7c1354bv25/cy7c1356bv25 incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this port operates in accordance with ieee standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. these functions fr om the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram . note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 2.5v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is ac tive depending upon the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected betw een the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. da ta is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output pins on the sram. seve ral no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. th e 36 configuration has a 69-bit-long register, and the 18 configurat ion has a 69-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully im plemented. the tap controller cannot be used to load address, data, or control signals into the sram and cannot preload the input or output buffers. the sram does not implement the 1149.1 commands extest or intest or the preload po rtion of sample/preload;
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 11 of 27 rather it performs a capture of the inputs and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instructi on register is loaded with all 0s. extest is not implemented in the tap controller, and therefore this device is not compliant to the 1149.1 standard. the tap controller does recogn ize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. unlike the sa mple/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr st ate. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction caus es the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 ma ndatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1-compliant. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the ta p may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar antee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/p reload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 12 of 27 note: 9. the 0/1 next to each state represents the value at tms at the rising edge of tck. tap controller state diagram [9] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-dr shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 13 of 27 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 68 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range [10, 11] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ?2.0 ma 1.7 v v oh2 output high voltage i oh = ?100 a2.0v v ol1 output low voltage i ol = 2.0 ma 0.7 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 1.7 v dd + 0.3 v v il input low voltage ?0.3 0.7 v i x input load current gnd v i v ddq ?30 30 a i x input load current tms and tdi gnd v i v ddq ?30 30 a tap ac switching characteristics over the operating range [12, 13] parameter descrip tion min. max. unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns notes: 10. all voltage referenced to ground. 11. overshoot: v ih (ac) < v dd + 1.5v for t < t tcyc /2; undershoot: v il (ac) > ? 0.5v for t < t tcyc /2. 12. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 13. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 14 of 27 t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test conditions tap ac switching characteristics over the operating range (continued) [12, 13] parameter descrip tion min. max. unit (a) tdo c l = 20 pf z 0 = 50 ? gnd 50 ? test clock test mode select tck tms test data-in tdi test data-out t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdov t tdox tdo 1.25v for 2.5v v ddq 2.5v v ss all input pulses 1.25v 1.5 ns 1.5 ns
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 15 of 27 identification register definitions instruction field cy7c1354bv25 cy7c1356bv25 description revision number (31:29) 001 001 reserved for version number. cypress device id (28:12) 01011001000100110 01011001000010110 reserved for future use. cypress jedec id (11:1) 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 indicat e the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 69 identification codes instruction code description extest 000 captures the input/output ring contents. pl aces the boundary scan regi ster between the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/outpu t contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instru ction is reserved for future use. sample/preload 100 captures the input/ou tput ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this inst ruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use: this instru ction is reserved for future use. reserved 110 do not use: this instru ction is reserved for future use. bypass 111 places the bypass register between tdi and td o. this operation does not affect sram operation.
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 16 of 27 boundary scan exit order (36) bit # 119-ball id 165-ball id 1k4 b6 2h4 b7 3m4 a7 4f4 b8 5b4 a8 6g4 a9 7c3 b10 8b3 a10 9d6 c11 10 h7 e10 11 g6 f10 12 e6 g10 13 d7 d10 14 e7 d11 15 f6 e11 16 g7 f11 17 h6 g11 18 t7 h11 19 k7 j10 20 l6 k10 21 n6 l10 22 p7 m10 23 n7 j11 24 m6 k11 25 l7 l11 26 k6 m11 27 p6 n11 28 t4 r11 29 a3 r10 30 c5 p10 31 b5 r9 32 a5 p9 33 c6 r8 34 a6 p8 35 p4 r6 36 n4 p6 37 r6 r4 38 t5 p4 39 t3 r3 40 r2 p3 41 r3 r1 42 p2 n1 43 p1 l2 44 l2 k2 45 k1 j2 46 n2 m2 47 n1 m1 48 m2 l1 49 l1 k1 50 k2 j1 51 not bonded (preset to 1) not bonded (preset to 1) 52 h1 g2 53 g2 f2 54 e2 e2 55 d1 d2 56 h2 g1 57 g1 f1 58 f2 e1 59 e1 d1 60 d2 c1 61 c2 b2 62 a2 a2 63 e4 a3 64 b2 b3 65 l3 b4 66 g3 a4 67 g5 a5 68 l5 b5 69 b6 a6 boundary scan exit order (36) (continued) bit # 119-ball id 165-ball id
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 17 of 27 boundary scan exit order (18) bit # 119-ball id 165-ball id 1k4 b6 2h4 b7 3m4 a7 4f4 b8 5b4 a8 6g4 a9 7c3 b10 8b3 a10 9t2 a11 10 not bonded (preset to 0) not bonded (preset to 0) 11 not bonded (preset to 0) not bonded (preset to 0) 12 not bonded (preset to 0) not bonded (preset to 0) 13 d6 c11 14 e7 d11 15 f6 e11 16 g7 f11 17 h6 g11 18 t7 h11 19 k7 j10 20 l6 k10 21 n6 l10 22 p7 m10 23 not bonded (preset to 0) not bonded (preset to 0) 24 not bonded (preset to 0) not bonded (preset to 0) 25 not bonded (preset to 0) not bonded (preset to 0) 26 not bonded (preset to 0) not bonded (preset to 0) 27 not bonded (preset to 0) not bonded (preset to 0) 28 t6 r11 29 a3 r10 30 c5 p10 31 b5 r9 32 a5 p9 33 c6 r8 34 a6 p8 35 p4 r6 36 n4 p6 37 r6 r4 38 t5 p4 39 t3 r3 40 r2 p3 41 r3 r1 42 not bonded (preset to 0) not bonded (preset to 0) 43 not bonded (preset to 0) not bonded (preset to 0) 44 not bonded (preset to 0) not bonded (preset to 0) 45 not bonded (preset to 0) not bonded (preset to 0) 46 p2 n1 47 n1 m1 48 m2 l1 49 l1 k1 50 k2 j1 51 not bonded (preset to 1) not bonded (preset to 1) 52 h1 g2 53 g2 f2 54 e2 e2 55 d1 d2 56 not bonded (preset to 0) not bonded (preset to 0) 57 not bonded (preset to 0) not bonded (preset to 0) 58 not bonded (preset to 0) not bonded (preset to 0) 59 not bonded (preset to 0) not bonded (preset to 0) 60 not bonded (preset to 0) not bonded (preset to 0) 61 c2 b2 62 a2 a2 63 e4 a3 64 b2 b3 65 not bonded (preset to 0 not bonded (preset to 0) 66 g3 not bonded (preset to 0) 67 not bonded (preset to 0 a4 68 l5 b5 69 b6 a6 boundary scan exit order (18) (continued) bit # 119-ball id 165-ball id
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 18 of 27 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v dd relative to gnd........ ?0.5v to +3.6v dc to outputs in three-state ............... ?0.5v to v ddq + 0.5v dc input voltage....................................?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature v dd /v ddq commercial 0c to +70c 2.5v + _5% industrial ?40c to +85c electrical characteristics over the operating range [14, 15] parameter description test conditions min. max. unit v dd power supply voltage 2.375 2.625 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage v dd = min., i oh = ? 1.0 ma 2.0 v v ol output low voltage v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [14] v ddq = 2.5v ?0.3 0.7 v i x input load current gnd v i v ddq ?5 5 a input current of mode ?30 30 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 4.4-ns cycle, 225 mhz 250 ma 5-ns cycle, 200 mhz 220 ma 6-ns cycle, 166 mhz 180 ma i sb1 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = f max = 1/t cyc all speed grades 50 ma i sb2 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades 35 ma i sb3 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = f max = 1/t cyc all speed grades 50 ma i sb4 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = 0 all speed grades 40 ma shaded areas contain advance information. capacitance [16] parameter description test conditions bga max. fbga max. tqfp max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 2.5v v ddq = 2.5v 555pf c clk clock input capacitance 5 5 5 pf c i/o input/output capacitance 7 7 5 pf notes: 14. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac)> -2v (pulse width less than t cyc /2). 15. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200ms. during this time v ih < v dd and v ddq < v dd .
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 19 of 27 thermal resistance [16] parameters description test conditions bga typ. fbga typ. tqfp typ. unit notes q ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 25 27 25 c/w 17 q jc thermal resistance (junction to case) 669 c/w 17 switching characteristics over the operating range [ 21, 22] parameter description -225 -200 -166 unit min. max. min. max. min. max. t power [17] v cc (typical) to the first access read or write 1 11ms clock t cyc clock cycle time 4.4 56ns f max maximum operating frequency 225 200 166 mhz t ch clock high 1.8 2.0 2.4 ns t cl clock low 1.8 2.0 2.4 ns output times t co data output valid after clk rise 2.8 3.2 3.5 ns t eov oe low to output valid 2.8 3.2 3.5 ns t doh data output hold after clk rise 1.25 1.5 1.5 ns t chz clock to high-z [18, 19, 20] 1.25 2.81.53.21.53.5 ns t clz clock to low-z [18, 19, 20] 1.25 1.5 1.5 ns t eohz oe high to output high-z [18, 19, 20] 2.8 3.2 3.5 ns t eolz oe low to output low-z [18, 19, 20] 0 00ns set-up times t as address set-up before clk rise 1.4 1.5 1.5 ns t ds data input set-up before clk rise 1.4 1.5 1.5 ns t cens cen set-up before clk rise 1.4 1.5 1.5 ns t wes we , bw x set-up before clk rise 1.4 1.5 1.5 ns t als adv/ld set-up before clk rise 1.4 1.5 1.5 ns shaded areas contain advance information. notes: 16. tested initially and after any design or proc ess changes that may affect these parameters. 17. this part has a voltage regulator internally; t power is the time power needs to be supplied above v dd minimum initially, before a read or write operation can be initiated. 18. t chz , t clz , t eolz , and t eohz are specified with ac test conditions shown in (b) of ac test loads. transition is measured 200 mv from steady-state voltage . 19. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention betw een srams when sharing the same data bus. these specifications do not imply a bus contention c ondition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 20. this parameter is sampled and not 100% tested. 21. timing reference level is 1.5v when v ddq = 2.5v. 22. test conditions shown in (a) of ac test loads unless otherwise noted. output r=1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25v 2.5v all input pulses [16] v dd 0v 90% 10% 90% 10% < 1.0 ns < 1.0 ns (c) ac test loads and waveforms 1.25v
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 20 of 27 t ces chip select set-up 1.4 1.5 1.5 ns t ah address hold after clk rise 0.4 0.5 0.5 ns hold times t dh data input hold after clk rise 0.4 0.5 0.5 ns t cenh cen hold after clk rise 0.4 0.5 0.5 ns t weh we , bw x hold after clk rise 0.4 0.5 0.5 ns t alh adv/ld hold after clk rise 0.4 0.5 0.5 ns t ceh chip select hold after clk rise 0.4 0.5 0.5 ns switching characteristics over the operating range (continued) [ 21, 22] parameter description -225 -200 -166 unit min. max. min. max. min. max. switching waveforms notes: 23. for this waveform zz is tied low. 24. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high,ce 1 is high or ce 2 is low or ce 3 is high. 25. order of the burst sequence is determined by the status of th e mode (0=linear, 1=interleaved).burst operations are optional. write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds data i n-out (dq) t clz d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t doh t chz t co write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz t doh don?t care undefined q(a6) q(a4+1) read/writetiming [23,24,25]
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 21 of 27 nop,stall and deselect cycles [23,24,26] note: 26. the ignore clock edge or stall cycle (clock 3) illustrated cen being used to create a pause. a wr ite is not perform ed during this cycle switching waveforms (continued) read q(a3) 456 78910 clk ce we cen bw x adv/ld address a3 a4 a5 d(a4) data in-out (dq) a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect don?t care undefined t chz a2 d(a1) q(a2) q(a3)
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 22 of 27 note: 27. device must be deselected when entering zz mode. see cycle descr iption table for all possible signal conditions to deselect the device. 28. i/os are in high-z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only zz mode timing [27, 28]
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 23 of 27 ordering information speed (mhz) ordering code package name package type operating range 225 cy7c1354bv25-225ac a101 100-lead thin quad flat pack (14 x 20 x 1.4 mm) commercial CY7C1356BV25-225ac cy7c1354bv25-225ai a101 100-lead thin quad flat pack (14 x 20 x 1.4 mm) industrial CY7C1356BV25-225ai cy7c1354bv25-225bgc bg119 119-ball ball grid array (14 x 22 x 2.4 mm) commercial CY7C1356BV25-225bgc cy7c1354bv25-225bgi bg119 119-ball ball grid array (14 x 22 x 2.4 mm) industrial CY7C1356BV25-225bgi cy7c1354bv25-225bzc bb165a 165-ball fine pitch ball grid array (13 x 15 x 1.2 mm) commercial CY7C1356BV25-225bzc cy7c1354bv25-225bzi bb165a 165-ball fine pitch ball grid array (13 x 15 x 1.2 mm) industrial CY7C1356BV25-225bzi 200 cy7c1354bv25-200ac a101 100-lead thin quad flat pack (14 x 20 x 1.4 mm) commercial cy7c1356bv25-200ac cy7c1354bv25-200ai a101 100-lead thin quad flat pack (14 x 20 x 1.4 mm) industrial cy7c1356bv25-200ai cy7c1354bv25-200bgc bg119 119-ball ball grid array (14 x 22 x 2.4 mm) commercial cy7c1356bv25-200bgc cy7c1354bv25-200bgi bg119 119-ball ball grid array (14 x 22 x 2.4 mm) industrial cy7c1356bv25-200bgi cy7c1354bv25-200bzc bb165a 165-ball fine pitch ball grid array (13 x 15 x 1.2 mm) commercial cy7c1356bv25-200bzc cy7c1354bv25-200bzi bb165a 165-ball fine pitch ball grid array (13 x 15 x 1.2 mm) industrial cy7c1356bv25-200bzi 166 cy7c1354bv25-166ac a101 100-lead thin quad flat pack (14 x 20 x 1.4 mm) commercial cy7c1356bv25-166ac cy7c1354bv25-166ai a101 100-lead thin quad flat pack (14 x 20 x 1.4 mm) industrial cy7c1356bv25-166ai cy7c1354bv25-166bgc bg119 119-ball ball grid array (14 x 22 x 2.4 mm) commercial cy7c1356bv25-166bgc cy7c1354bv25-166bgi bg119 119-ball ball grid array (14 x 22 x 2.4 mm) industrial cy7c1356bv25-166bgi cy7c1354bv25-166bzc bb165a 165-ball fine pitch ball grid array (13 x 15 x 1.2 mm) commercial cy7c1356bv25-166bzc 166 cy7c1354bv25-166bzi bb165a 165-ball fine pitch ball grid array (13 x 15 x 1.2 mm) industrial cy7c1356bv25-166bzi shaded areas contain advance information. plea se contact your local cypress sales repr esentative for availability of these part s.
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 24 of 27 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 25 of 27 package diagrams (continued) 51-85115-*b 119-lead bga (14 x 22 x 2.4mm) bg119
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 26 of 27 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. zbt is a registered trademark of integrated device technolo gy. no bus latency and nobl ar e trademarks of cypress semicon- ductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 51-85122-*c 165-ball fbga (13 x 15 x 1.2 mm) bb165a
cy7c1354bv25 cy7c1356bv25 document #: 38-05292 rev. *e page 27 of 27 document history page document title: cy7c1354bv25/cy7c1356bv25 256k x 36 /512k x 18 pipelined sram with nobl? architecture document number: 38-05292 rev. ecn no. issue date orig. of change description of change ** 114767 08/08/02 rcs new data sheet *a 117938 08/20/02 rcs added a0 and a1 to 165 fbga pinout *b 126206 04/11/03 dpm removed preliminary status removed 250-mhz speed bin added 225-mhz speed bin increased t co , t eov , t chz , t eohz for 200 mhz to 3.2 ns from 3.0 ns updated jtag revision number and device depth updated jtag boundary scan orders added t power specification changed footnotes ordering added industrial operating range changed capacitance table to have tqfp, bga, and fbga columns *c 206704 see ecn njy removed footnote 13 ? minimum voltage equals ?2.0v for pulse durations of less than 20 ns.? removed footnote 14 ? ta is the case temperature.? changed footnote 15 from ? overshoot: v ih (ac) < v dd + 1.5v for t < t tcyc /2; undershoot: v il (ac) < 0.5v for t < ttcyc/2; power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ms ? to footnote 13 ? overshoot: v ih (ac) < v dd +1.5v (pulse width less than tcyc/2), undershoot: vil(ac)> -2v (pulse width less than tcyc/2) ? added footnote 14 ? t power-up : assumes a linear ramp from 0v to v dd (min.) within 200ms. during this time v ih < v dd and v ddq < v dd ? changed footnote 20 from ? test conditions shown in (a), (b) and (c) of ac test loads ? to ? test conditions shown in (a) of ac test loads unless otherwise noted ? updated zz mode electrical characteristics updated i sb1 and i sb3 currents in electrical characteristics table updated the test condition in thermal resistance table updated ordering information *d 239272 see ecn vbl changed bit #24 on id register definitions on page 15 from ?0? to ?1? update ordering info *e 280209 see ecn njy changed balls b4 and a5 from bw d and bw b to nc and ball a4 from bw c to bw b for 165-ball fbga package for cy7c1356bv25 changed balls c11 from dqpb to dqpa and balls d11,e11,f11 and g11 from dqb to dqa for cy7c1356bv25.

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